Integrated circuits are widely used in consumer and industrial products. As is well known to those having skill in the art, integrated circuit devices, including but not limited to logic, memory and microprocessor devices, may include up to one million or more Field Effect Transistors (FETs). As the integration density of integrated circuits continues to increase, the size of the individual field effect transistors generally decreases. For example, the integration density of each succeeding generation of integrated circuits may increase by a factor of four. The dimensions of the field effect transistors, including a length of the channels thereof, may also decrease by a factor of four.
As the integration density of field effect transistors continues to increase, various "short channel effects" such as sub-threshold leakage and threshold variations may occur. Many techniques have been proposed to reduce short channel effects in submicron field effect transistors. For example, a surface implant may be used to control the threshold voltage of the field effect transistor. Contoured buried implants beneath the source and drain regions may also be used to reduce punch-through effects.
FIGS. 1 and 2 are cross-sectional views illustrating field effect transistors that may include additional regions to reduce short channel effects. Specifically, FIG. 1 illustrates a field effect transistor including spaced apart source and drain regions 14 in an integrated circuit substrate, such as a semiconductor substrate. A gate insulating layer, such as a gate oxide layer 12, and a gate electrode 13, such as a polysilicon gate electrode, are formed on the integrated circuit substrate between the spaced apart source and drain regions. Field oxide regions 11 isolate the field effect transistor. As shown in FIG. 1, a surface implant region 100 is formed by implanting ions into the semiconductor substrate before fabricating the gate oxide layer 12, the gate electrode 13 and the source/drain regions 14. The surface implant region 100 may be used to control the threshold voltage of the field effect transistor.
FIG. 2 is a cross-sectional view of another field effect transistor that includes a surface implant 100 to control threshold voltage and contoured buried implants 200 to reduce punch-through. As shown in FIG. 2, the contoured buried implants 200 are formed adjacent the bottoms of the source/drain regions 14.
Unfortunately, the formation of the surface implants and/or the contoured buried implants to overcome short channel effects may degrade the reliability of the gate oxide layer 12. In submicron field effect transistors, the gate oxide layer may be extraordinarily thin, and therefore may be more susceptible to degradation than in earlier generations of field effect transistors that employ relatively thick gate oxides.